DocumentCode
2355155
Title
Design-space exploration of fault-tolerant building blocks for large-scale quantum computing
Author
Metodi, Tzvetan S. ; Cross, Andrew W. ; Thaker, Darshan D. ; Chuang, Isaac L. ; Chong, Frederic T.
Author_Institution
Univ. of California at Davis, Davis, CA
fYear
2007
fDate
21-22 Oct. 2007
Firstpage
7
Lastpage
14
Abstract
In this paper, we present a design methodology for quantifying the role each building component of a logical fault-tolerant building block for quantum computers plays in the performance of the logical block. A logical building block is the set of operations necessary to execute a fault-tolerant circuit structure in quantum programs, such as the network of operations implementing a logical quantum bit. By analyzing the interaction between the algorithmic structure of a building block and the number of lower-level elements where faults are likely to occur, we can quantify the sensitivity of logical building blocks to two things: (1) to changes in the failure rates of the lower level elements comprising a proposed microarchitecture model, which are defined as logic gates, memory mechanisms, and data communication mechanisms; and (2) to transformation of the program structure for each building block through compilation techniques. We further show how this information can be used to develop optimized building blocks by inserting the gathered design constraints in our compilation mechanisms.
Keywords
computer architecture; fault tolerant computing; large-scale systems; logic design; quantum gates; sensitivity; data communication mechanisms; large-scale quantum computing; logic gates; logical fault-tolerant building blocks; memory mechanisms; microarchitecture model; sensitivity; space exploration; Algorithm design and analysis; Buildings; Circuit faults; Design methodology; Failure analysis; Fault tolerance; Large-scale systems; Logic gates; Microarchitecture; Quantum computing; fault-tolerant; quantum; sensitivity;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanoscale Architectures, 2007. NANOSARCH 2007. IEEE International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-1790-2
Electronic_ISBN
978-1-4244-1791-9
Type
conf
DOI
10.1109/NANOARCH.2007.4400851
Filename
4400851
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