Design considerations for a pyramidal cellular logic processor

A massively parallel pyramid processor for performing low-level image processing is discussed. The processor is designed from the ground up with the goal of providing a set of single-instruction multiple-data (SIMD) pyramid operations useful to programs written in a high-level language for eventual feature extraction. The approach begins with a consideration of the operations required to support typical vision operations and embeds these operations in the C programming language as parallel constructs. A compiler for this extended C (called HCL, for hierarchical cellular logic) defines the set of low-level pyramid operations required for a pyramidal cellular processor. This instruction set defines the microarchitecture of the processor elements and the capabilities of the controller. A study of mid-level processing algorithms and the properties of edges in an image results in the definition of fast parallel hardware for searching edge maps in order to create graph structures for high-level processing