Device mismatch limitations on performance of a Hamming distance classifier

Author

Kumar, Nagendra ; Pouliquen, Philippe O. ; Andreou, Andreas G.

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

fYear

1993

fDate

27-29 Oct 1993

Firstpage

327

Lastpage

334

Abstract

The performance of a memory based computational engine, a Hamming distance classifier that employs static memory cells and an analog Winner-Takes-All circuit depends on device matching in the various parts of the circuit. This dependence has been analyzed, leading to design criteria for choosing the device sizes and chip structure. The theoretical performance of a CMOS chip designed to operate in the subthreshold and transition region has been compared with the actual experimental results

Keywords

VLSI; CMOS chip; Hamming distance classifier; NMOS; PMOS; VLSI; analog Winner-Takes-All circuit; chip structure; design criteria; device sizes; exclusive-OR static memory; matching; memory based computational engine; mismatch limitations; performance; static memory cells; subthreshold region; transition region; Analog computers; Biology computing; Circuit testing; Computer interfaces; Fault tolerant systems; Hamming distance; Neural networks; Pattern matching; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on

Conference_Location

Venice

ISSN

1550-5774

Print_ISBN

0-8186-3502-9

Type

conf

DOI

10.1109/DFTVS.1993.595829

Filename

595829