A wafer level through-stack-via integration process with one-time bottom-up copper filling

We reported a wafer level through-stack-via (TSV) integration approach for stacked memory module using onetime bottom-up copper filling. This bumpless TSV integration approach simplified the fabrication process and provided better reliability compared with solder based technologies. Silicon wafer with blind vias was first bonded to a carrier wafer face to face with pre-patterned BCB, and then thinned from backside to reveal the TSVs. The carrier wafer was coated with a release layer and a seed layer, which provided a uniform seed layer for bottom-up TSV filling and was easy to be debonded. A layer of copper RDL was pre-deposited on the silicon wafer before bonding, which enhanced the wettability of the sidewall of TSVs during bottom-up copper filling. More silicon wafers could be bonded and thinned in the same way. At last, one-time bottom-up TSV filling was performed and the carrier wafer was released. A 4-layer wafer stacking with TSVs of 173μm × 52μm has been successfully demonstrated with the thinnest wafer of 22μm. The electrical test results shown that this process had a significant yield improvement. The lowest resistance measured was 7.6mΩ with the yield of over 84% on the 4-inch wafer. This proposed TSV integration process was ready for stacked memory application.