Design and analysis of multi-gigahertz parallel bus interfaces of low-cost and band-limited channels

The further scaling of chip performance into multi-gigabit data rates puts special demands on the bandwidth of interconnect systems. This leads to the need for careful optimization of the parameters of the channel and the components along the path of the signal and the need of special circuitry in transceivers to mitigate the effects of the band-limited channels. This paper characterizes various bandwidth limiting factors in a low-cost interconnect system and evaluates equalization techniques that are needed to overcome the limitations to improve the interconnect system performance at multi-gigabit data rates. The sensitivity of equalization taps to manufacturing variations in channel parameters is also studied. Finally, detailed analyses of low-cost and high-speed memory operating at 3.2 Gbps and logic-to-logic interconnect systems operating at 6.4 Gbps are presented to illustrate the effectiveness of equalization techniques.