Overlay-NoC and H-Phy based computing using modern Chip Multiprocessors

Constant growth in demand for computational power requires advances in the internal mechanisms of multiprocessor computing structures. Such architectures may include many (sometimes, even millions of) processors performing processing tasks. Each technique that increases efficiency leads to significant benefits in operational energy and task execution time. Due the scale of multiprocessor computing structures, the importance of achieving faster and efficient systems is invaluable. In this paper, we present two different approaches for processing tasks on multiprocessor architectures: Hardware-Physical (H-Phy) and Overlay-Network-on-Chip (Overlay-NoC). Both methods are described and compared. We also present the research plan, models, simulation assumptions, and results of research. The paper is summarized with conclusions and future work plan.