Methodology and apparatus for rapid power cycle accumulation and in-situ incipient failure monitoring for power electronic modules

Power cycling lifetime is a topic of continued interest in the power electronic module industry. For inverter power modules consisting of IGBT and diode power devices, wear-out mechanisms usually encountered are wirebond lift and solder joint degradation. Wirebond failures typically manifest in an upward shift in V_ce(sat) well before an open circuit condition occurs. Solder joint degradation usually manifests as an increase in die temperature that may be detected by a calculation of thermal impedance. Design and manufacturing processes have matured so that highly reliable, high quality modules are available from numerous manufacturers. However, the burden still remains on manufacturers to demonstrate the power cycling lifetime of their products. Given the range of application conditions to which power modules may be exposed, it is beneficial to customers for manufacturers to provide power cycling lifetime data in terms of number of cycles to failure for various levels of delta-T_j and various starting temperatures, T₀. It is also beneficial, during design cycles, for module designers and manufacturing engineers to obtain quantified failure data on prototype designs regarding onset of the failure mechanisms mentioned. In this paper, we describe and demonstrate a method for the rapid accumulation of delta-T_j cycles under various conditions and develop in-situ monitoring methods for V_ce(sat) and V_f which are of sufficient accuracy to detect incipient failures in the module, and which do not require the cessation of power cycling to perform a readout. In particular, a three phase inverter module consisting of six IGBTs and six anti-parallel diodes is tested in a multimodule, multi-operating point test stand. Three phase inductive loading with typical switching frequency and various amplitude sinusoidal current profiles is carried out under controlled starting temperatures for each module, while monitoring- V_ce(sat), diode V_f, and module substrate temperature. The V_ce(sat) and V_f are sampled at instants of known phase current so as to correlate with nominal device behavior in order to determine health of the wirebond and solder interfaces. Module control, data acquisition, load determination, failure detection, and data logging are described. Simulation techniques used to target the operating conditions necessary to achieve a particular delta-T_j are shown, along with experimental data used to validate these simulations. Experimental results from the power cycling to date are shown.