Bump pattern optimization and stress comparison study for DCA packages

With the increasing demand for reduced package size and enhanced package performance, the semiconductor industry has intensified focus on the development of alternate technologies, resulting in significant interest in flip chip or direct chip attach (DCA) packages using copper pillar bump interconnects. In DCA packages, the coefficient of thermal expansion (CTE) mismatch between different materials causes warpage/reliability issues during the reflow process and thermal cycling. These CTE mismatch issues interact with various copper pillar patterns and affect package reliability. This study reports on simulation work to optimize the 1st level copper pillar patterns on DCA packages. Finite element models have been established to understand the effects of various copper pillar patterns on stress conditions in solder regions. In addition to material factors like low CTE core and different underfill compounds, other factors including solder joint thickness, a portion of the copper pillar bumps and die thickness are also simulated to determine the impact on solder stress in relation to the die and substrate interface.