DocumentCode
2355803
Title
Integrated power grid modeling and analysis
Author
Wang, Yong ; Quint, Dave ; Fetzer, E.
Author_Institution
Fort Collins Microelectron. Lab., CO, USA
fYear
2003
fDate
27-29 Oct. 2003
Firstpage
325
Lastpage
328
Abstract
This paper presents a new approach for the integrated power grid modeling and analysis. A loop-based inductance model is used to simplify the package and on-chip circuit model. A more accurate on-chip load model is created for current and future IC processes.
Keywords
RLC circuits; SPICE; capacitance; circuit layout CAD; circuit simulation; inductance; integrated circuit layout; integrated circuit modelling; integrated circuit packaging; power supply circuits; IC processes; RLC model; SPICE simulation; integrated power grid modeling; intrinsic capacitance model; loop-based inductance model; on-chip circuit model; on-chip load model; package design; power delivery system; Inductance; Integrated circuit modeling; Packaging; Performance analysis; Power grids; Power supplies; Power system modeling; RLC circuits; System-on-a-chip; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 2003
Conference_Location
Princeton, NJ, USA
Print_ISBN
0-7803-8128-9
Type
conf
DOI
10.1109/EPEP.2003.1250060
Filename
1250060
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