DocumentCode
235581
Title
Characterization of in-plane stress in TSV array — A unit model approach
Author
Cheng-fu Chen
Author_Institution
Dept. of Mech. Eng., Univ. of Alaska Fairbanks, Fairbanks, AK, USA
fYear
2014
fDate
27-30 May 2014
Firstpage
2020
Lastpage
2026
Abstract
This paper presents an analytical model to describe the in-plane thermomechanical stresses of a unit TSV model. The goal is to use this model to evaluate the influence of key design parameters in TSV interposers prior to rigorous investigations. The key parameters considered herein are via pitch and array size. This analytical model is based on a circular unit TSV structure, the size of which (in terms of its radius R) determines both the via´s volume fraction and the behavior of the stress. The value of R can be V(Aft), where A is the area of a unit polygonal pattern in a fabricated TSV array. With a superposition of many such unit TSV structures at a given pitch, we illustrate the stress-interplay issue that becomes apparent in densely populated TSVs. We also use this simple strategy to highlight the stress concentration at the Cu/Si interface, which is critical to thermomechanical reliability design of TSV interposers.
Keywords
copper; integrated circuit reliability; silicon; thermomechanical treatment; three-dimensional integrated circuits; Cu-Si; Cu-Si interface; TSV array; TSV interposers; analytical model; circular unit TSV structure; in-plane stress; in-plane thermomechanical stresses; stress concentration; stress-interplay; thermomechanical reliability; unit model approach; unit polygonal pattern; via array size; via pitch size; via volume fraction; Analytical models; Arrays; Load modeling; Silicon; Stress; Thermomechanical processes; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location
Orlando, FL
Type
conf
DOI
10.1109/ECTC.2014.6897580
Filename
6897580
Link To Document