TSV CMP process optimization and dishing defect reduction

Three-dimensional (3D) chip integration is one of the most important and main trends in the advance packaging technology for this technology could reduce interconnect delay, increase bandwidth, lower power consumption, lower cost and heterogeneous integration possibility. This technology calls for the stacking of integrated circuits interconnected by through silicon via (TSV). The TSV special structure required the CMP process with higher Cu removal rate, low dishing and good topography performance. In this paper, Via-middle TSV dishing performance had been investigated in 300mm wafer. To obtain a minimum Cu dishing on the TSV region, two kinds of commercial slurry and one formulation slurry had evaluated for Cu removal rate and post Cu removed dishing performance. Moreover, the influence of via-diameter on dishing had also been investigated in the paper. Based on the tested result screen a high Cu removal rate and low dishing slurry, by optimized CMP polish process parameters (multi-polish with different down pressure, pad/platen rotation), to obtain a robust via-middle TVS CMP process.