Power distribution network worst-case power noise and an efficient estimation method

In this study, we examine a novel insight into the worst-case power noise in power integrity analysis for the core power of an ASIC. It is found that the traditional target impedance method resorting minimizing the peak impedance cannot guarantee a minimal worst-case power noise. The reason is because the worst-case power noise may not occur when the ASIC switching current is modulated at the peak impedance frequency of the power delivery network, contrary to what has been suggested in other studies. This paper discusses the fundamental mechanism behind this phenomenon. Additionally, we propose a new guideline to assess the worst-case power noise, i.e., characterizing the relationship between the power noise and the modulation frequency of the switching current. An efficient method to quickly characterize the relationship is provided, which is capable of greatly reducing the simulation time to reveal the `true´ worst-case power noise.