Electrical simulation and analysis of Si interposer for 3D IC integration

This paper focuses on the electrical simulation and analysis of silicon interposer. Basic interconnect elements such as TSV and RDL are simulated and verified with measurement results, electrical parameters are extracted and analyzed. Segmentation is used in long signal path modeling to improve simulation efficiency with a fine accuracy. Silicon interposer is segmented into many interconnect pieces. Parasitic RLCGs of each segment are extracted and interconnected to form the whole circuit model of Si interposer. A Silicon interposer for a 4-SRAM module integration, proposed and implemented as a leading demo for a Logic+Memory high-speed digital signal processing module, was used as a test vehicle for the modeling and analysis methodologies mentioned.