Title :
On the test and diagnosis of the perfect shuffle
Author :
Schiano, L. ; Lombardi, F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
In this paper, a new structural approach is proposed for the full diagnosis (with no aliasing and confounding) of shorts and stuck-at faults in the interconnect of a perfect shuffle. This approach utilizes graph coloring techniques to generate a test set based on the adjacencies in the largest necklace of the shuffle. The conditions for no aliasing and confounding as well as fault detection are presented as function of the largest short fault. For detecting stuck-at faults, it is shown that a constant number of tests is required. A test generation algorithm with quadratic execution complexity in the size of the shuffle is proposed. This algorithm generates a test set which diagnoses a perfect shuffle of size N with no aliasing and confounding using O(log2(log2 (N))) tests. The application of these results to multistage interconnection networks (MINs) is also presented: MINs can be constructed by cascading perfect shuffles and are characterized by switching operation. It is shown that constant testability of MINs can be still achieved for diagnosis under fault models which preserve the loop properties of the necklaces in a perfect shuffle.
Keywords :
automatic test pattern generation; cascade networks; circuit complexity; fault diagnosis; graph colouring; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; logic testing; multistage interconnection networks; MIN constant testability; adjacencies; aliasing conditions; cascading; confounding conditions; fault detection; fault diagnosis; fault models; graph coloring techniques; loop properties; multistage interconnection networks; perfect shuffle diagnosis; perfect shuffle interconnection networks; perfect shuffle necklace; quadratic execution complexity; short faults; shuffle size; structural approach; stuck-at faults; test generation algorithm; test set; Fault detection; Fault diagnosis; Multiprocessor interconnection networks; Testing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on
Print_ISBN :
0-7695-2042-1
DOI :
10.1109/DFTVS.2003.1250100