DocumentCode :
235636
Title :
PCIe Gen3 link design and tuning in server systems with end devices from multiple IP suppliers
Author :
Win, Si T. ; Rodriguez, David ; Nanju Na
Author_Institution :
IBM Syst. & Technol. Group, Austin, TX, USA
fYear :
2014
fDate :
27-30 May 2014
Firstpage :
2151
Lastpage :
2158
Abstract :
This paper discusses link routing budget considerations for PCIe Gen3 designs in server systems. Special attention will be given to channel discontinuities and their effect on eye opening. Link training complications will be discussed with respect to equalization and tuning behavior when accommodating multiple transmitters and receivers from different vendor sources. Insertion loss plots and eye simulation data will be analyzed and interpreted. Hardware data will show that optimally simulated equalization cases may not necessarily occur.
Keywords :
equalisers; peripheral interfaces; printed circuit interconnections; tuning; IP suppliers; PCIe Gen3 link design; channel discontinuities; eye opening; eye simulations; insertion loss plots; link routing budget; server systems; Adaptive equalizers; Connectors; Gain; Insertion loss; Routing; Topology; Training;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
Type :
conf
DOI :
10.1109/ECTC.2014.6897600
Filename :
6897600
Link To Document :
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