Power supply current test approach for resistive fault screening in embedded analog circuits

The feasibility of a non-specification based method for testing of analog integrated circuits in a 0.13 μm CMOS process has been explored. The method is an extension of digital I_DD test to analog circuits. We investigated detection rate of resistive open and short faults within a MOSFET device in several analog circuits implemented in 0.13 μm CMOS technology. Input test signals are optimized for maximum detectability of introduced faults. Stimuli required for defect screening are DC signals which can be easily produced on-chip. It is shown in this paper that with respect to the used fault models, the detection success rate for introduced faults is 100% for resistive shorts and 67% for resistive opens. This simple method is suitable for production testing, as a preliminary and complementary test of embedded analog circuits for early defect screening in highly integrated environment.