Title :
Constrained ATPG for broadside transition testing
Author :
Liu, Xiao ; Hsiao, Michael S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
Abstract :
In this paper we propose a new concept of testing only functionally testable transition faults in broadside transition testing via a novel constrained ATPG. For each functionally untestable transition fault f, a set of illegal (unreachable) states that enable detection of f is first computed. This set of undesirable illegal states is efficiently represented as a Boolean formula. Our constrained ATPG then incorporates this constraint formula to generate broadside vectors that avoid those undesirable states. In doing so, our method efficiently generates a rest set for functionally testable transition faults and minimizes detection of functionally untestable transition faults. Since we want to avoid launching and propagating transitions in the circuit that are not possible in the functional mode, a direct benefit of our method is the reduction of yield loss due to overtesting of these functionally untestable transitions.
Keywords :
automatic test pattern generation; failure analysis; fault location; integrated circuit testing; integrated circuit yield; logic testing; production testing; Boolean formula; broadside transition testing; constrained ATPG; functional mode; functionally testable transition fault test set; functionally testable transition faults; functionally untestable transition fault; illegal unreachable states; overtesting; undesirable illegal states; yield loss reduction; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Delay effects; Electrical fault detection; Fault detection; Flip-flops; Propagation delay; Propagation losses;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on
Print_ISBN :
0-7695-2042-1
DOI :
10.1109/DFTVS.2003.1250110