About the application of CMP for Monolithic integration of photonic components in a 0.25 μm BiCMOS process

We compare CMP process variants used for FEOL integration of photonic components in a SiGe BiCMOS baseline. These CMP variants are part of a process sequence yielding wafers with local SOI regions surrounded by bulk Si areas. This particular wafer structure allows one to fabricate low loss photonic devices like waveguides, couplers and modulators side by side with high-performance BiCMOS devices such as SiGe HBTs. Starting with SOI wafers with optimum vertical structure for photonic application, the original SOI layer stack is etched away at areas where bulk Si is required to form the BiCMOS devices. Selective Si epitaxy is then applied to fill up the etched regions with a few μm overgrowing. The purpose of the following Si-CMP step is to get a planar wafer structure with minimum height differences between SOI and bulk Si regions without big restrictions in their respective lateral dimensions. We discuss here in particular measures applied to fulfill this requirement, including the optimization of the CMP process itself and the use of an auxiliary, polycrystalline Si layer for a blind polish step.