Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation

When the code length is moderate, non-binary low-density parity-check (NB-LDPC) codes can achieve better error correcting performance than their binary counterparts at the expense of higher decoding complexity. The check node processing is a major bottleneck of NB-LDPC decoding. This paper proposes a novel scheme for the forward-backward check node processing by making use of the cyclical-shift property of the power representation of finite field elements. Compared to previous designs, the proposed check node units (CNUs) do not need the complex switching network. Moreover, the multiplications of the parity check matrix entries are efficiently incorporated. For a Min-max NB-LDPC decoder over GF(32), the proposed schemes reduce the CNU area by at least 32%, and lead to higher clock frequency than prior efforts.