Hybrid BIST using an incrementally guided LFSR

Author

Krishna, C.V. ; Touba, Nur A.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

2003

fDate

3-5 Nov. 2003

Firstpage

217

Lastpage

224

Abstract

A new hybrid BIST scheme is proposed which is based on using an "incrementally guided LFSR". It very efficiently combines external deterministic data from the tester with on-chip pseudo-random BIST. The hardware overhead is very small as a conventional STUMPS architecture (P. H. Bardell et al., Proc. Int. Test Conf., p.200-204, 1982) is used with only a small modification to the feedback of the LFSR which allows the tester to incrementally guide the LFSR so that it can embed patterns that detect the random-pattern-resistant faults in the pseudo-random sequence. Compared with external testing, the proposed approach achieves dramatic reductions in tester storage requirements while using very simple on-chip hardware. Results indicate that the proposed approach provides very attractive tradeoffs between test length and tester storage requirements.

Keywords

binary sequences; built-in self test; integrated circuit testing; logic design; logic testing; random sequences; LFSR feedback; STUMPS architecture; external deterministic tester data; fault coverage; hybrid BIST; incrementally guided LFSR; on-chip pseudo-random BIST; pseudo-random sequence; random-pattern-resistant faults; test length; tester storage requirement reduction; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Feedback; Hardware; Logic testing; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2042-1

Type

conf

DOI

10.1109/DFTVS.2003.1250115

Filename

1250115