Title :
A single error correcting and double error detecting coding scheme for computer memory systems
Author_Institution :
Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA
Abstract :
This paper proposes a new coding technique for single error correction and double error detection in computer memory systems. The number of 1s in the parity check matrix for the proposed coding is fewer than all currently available codes for this purpose. This results in simplified encoding and decoding circuitry for error detection and correction.
Keywords :
error correction codes; error detection codes; parity check codes; storage management; PCM; computer memory systems; decoding circuitry; double error detecting coding scheme; encoding circuitry; error correction; error detection; parity check matrix; single error correcting coding scheme; Circuits; Computer errors; Computer science; Decoding; Encoding; Error correction; Error correction codes; Parity check codes; Pattern matching; Phase change materials;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on
Print_ISBN :
0-7695-2042-1
DOI :
10.1109/DFTVS.2003.1250117
