Quadruple time redundancy adders [error correcting adder]

Author

Townsend, Whitney J. ; Abraham, Jacob A. ; Swartzlander, Earl E.

Author_Institution

Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA

fYear

2003

fDate

3-5 Nov. 2003

Firstpage

250

Lastpage

256

Abstract

This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, quadruple time redundancy, is compared with a non-redundant adder, a triple modular redundancy adder, and a time shared triple modular redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with time shared triple modular redundancy to which it is most closely related, quadruple time redundancy results in a 40%-55% reduction in hardware complexity while incurring a reasonable delay increase.

Keywords

adders; error correction; error detection; fault tolerance; redundancy; concurrent error correction; concurrent error detection; error correcting adder; fault masking; fault tolerance; hardware complexity; hardware redundancy; nonredundant adder; quadruple time redundancy adders; time shared triple modular redundancy adder; Added delay; Adders; Arithmetic; Circuits; Costs; Delay effects; Error correction; Fault tolerance; Hardware; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2042-1

Type

conf

DOI

10.1109/DFTVS.2003.1250119

Filename

1250119