Error correcting codes for crosstalk effect minimization [system buses]

In this paper, we present an analysis of crosstalk effects on buses implementing error correcting codes. We show that the redundancy introduced by these codes can be exploited in order to avoid the worst case crosstalk-induced delay. Our analysis is based on the evaluation of the coupling effective capacitance which needs to be charged during bus activity. In particular, we analyze the cases of the Hamming and dual rail codes. We show that Hamming codes do not allow us to avoid the most delay costly bus transitions, while this can be the case for dual rail codes. Furthermore, we illustrate that, by increasing the redundancy of the dual rail code by only one bit, even higher crosstalk-induced delay reductions can be achieved. Finally, we show that a further improvement can be obtained by an optimized placing of the bus wires.