BiST model for IC RF-transceiver front-end

Author

Dabrowski, Jerzy

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Sweden

fYear

2003

fDate

3-5 Nov. 2003

Firstpage

295

Lastpage

302

Abstract

In this paper, a BiST technique for an RF transceiver front-end is presented. The test is aimed at spot defects typical of mass production in the CMOS process. The loop-back approach is used to detect faults modeled as resistive breaks or bridges. The resulting impairment in gain, noise figure or selectivity of the RF blocks are considered functional-level faults, and as such are subjected to test with PRBS stimulus and BER as the response at base-band. The extra test circuitry is limited and the on-chip resources are used to set-up the BiST. A model of a GSM transceiver with BiST is investigated to verify the proposed approach.

Keywords

CMOS integrated circuits; built-in self test; cellular radio; error statistics; integrated circuit modelling; integrated circuit testing; radiofrequency integrated circuits; transceivers; BER; BiST model; CMOS process; GSM transceiver; PRBS stimulus test; RF block selectivity; RF-transceiver front-end; RFIC; base-band response; bridges; fault detection; functional-level faults; gain impairment; loop-back method; noise figure; resistive breaks; spot defects; CMOS process; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit modeling; Mass production; Radio frequency; Semiconductor device modeling; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2042-1

Type

conf

DOI

10.1109/DFTVS.2003.1250124

Filename

1250124