Effective processor array architecture with shared memory

In this paper, we propose a new processor array architecture with effective data storage schemes and its design methodology. The array, called the Memory Sharing Processor Array (MSPA), consists of a processor array with several memory units and their address generation hardware units in order to minimize the data storage. MSPA architecture and its design methodology is similar to the conventional systolic array, but tries to overcome the overlapping data storages, idle processing time and the I/O bottleneck, which mostly degrade the performance of the systolic array. It has practical advantages over the systolic array with regard to area-efficiency, high throughput and practical input schemes. If the number of the concurrent data input ports is limited in a practical situation, the systolic array does not work efficiently. MSPA uses the data access scheme of the common bus architecture, but limits its usage only when it does not cause any data access bottleneck