DocumentCode
2356955
Title
Architecture driven computational ordering and code generation method for DSP compiler
Author
Vilasdechanon, Jirasuk ; Anurucks, Kiti Likit ; Sugino, Nobuhiko ; Nishihara, Akinori
Author_Institution
Dept. of Electr. Eng., Chiang Mai Univ., Thailand
fYear
1994
fDate
5-8 Dec 1994
Firstpage
157
Lastpage
161
Abstract
A computational ordering and code generation method for DSP compiler, which take the target DSP architecture, i.e., the number of accumulators, bus structure and multi-operation instruction code, into consideration is proposed. By combining computation ordering and code generation into one step, a better outcome code of DSP compiler may be obtained. Although only μPD 7720 is used as target DSP in this work, the method may be applied to other DSPs
Keywords
digital signal processing chips; parallel architectures; program compilers; μPD 7720; DSP compiler; architecture driven computational ordering; bus structure; code generation method; multi-operation instruction code; outcome code; target DSP architecture; Assembly; Computer architecture; Digital signal processing; Digital signal processing chips; Digital signal processors; Hardware; Program processors; Read only memory; Read-write memory; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Conference_Location
Taipei
Print_ISBN
0-7803-2440-4
Type
conf
DOI
10.1109/APCCAS.1994.514541
Filename
514541
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