Error detection in signed digit arithmetic circuit with parity checker [adder example]

This paper proposes a methodology for the development of simple arithmetic self-checking circuits using a signed digit representation. In particular, the architecture of an adder is reported and its self-checking capability with respect to the stuck-at fault set is shown. The main idea underlying the paper is to exploit the properties of signed digit representation, allowing carry-free operations. In a carry free adder, the parity can be easily checked, allowing therefore detecting the occurrence of a fault belonging to the considered stuck-at fault set. The proposed architecture is therefore very suitable for the implementation of self-checking adders that are also fast due to the same carry free property.