Digital design from concept to prototype in hours

In this paper, we present a behavior synthesis system, called MEBS, for digital system design and prototyping. MEBS takes a VHDL behavior description, synthesizes it into structure, and translates it into a format which is ready for FPGA or standard-cell implementation. A VHDL description of a circuit may be described as several communicating processes at various levels of abstraction including algorithmic level, finite state machine with datapath (FSMD) level, register transfer (RT) level, and logic gate level. The synthesis tasks include transformation, scheduling, allocation, RTL module synthesis, memory synthesis, sequential synthesis, and I/O interface generation. During the synthesis process, an intermediate result can be written out in VHDL format for simulation and read back for synthesis. We have used the system to prototype a set of benchmark examples. A digital design can be realized within hours using this system