Layout design considerations in MOS continuous-time integrated filters

Author

Smith, Shirley ; Ismail, Mohammed ; Hung, Chune-Chih ; Huang, Shu-Chuan

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

fYear

1994

fDate

5-8 Dec 1994

Firstpage

300

Lastpage

305

Abstract

Analysis of two layout designs used in the realization of MOS continuous-time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C_P/C, as a parameter. These graphs are useful in the design of high performance MOS continuous-time integrated filters

Keywords

MOS analogue integrated circuits; capacitance; circuit layout CAD; continuous time filters; harmonic distortion; integrated circuit layout; MOS continuous-time integrated filters; MOS parasitic capacitances; harmonic distortion; layout design; performance graphs; transistor matching; Cities and towns; Filters; Frequency; Harmonic distortion; MOSFET circuits; Operational amplifiers; Parasitic capacitance; Prototypes; Topology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on

Conference_Location

Taipei

Print_ISBN

0-7803-2440-4

Type

conf

DOI

10.1109/APCCAS.1994.514566

Filename

514566