An investigation of board level effects on compact thermal models of electronic chip packages

The application and use of Compact Thermal Models of single chip electronic packages in a board level environment has seen limited study. In particular the influence of board thermal characteristics on the predictive accuracy of CTMs generated independently of the board is not well understood. A systematic study of the influence of board conduction on the predictive accuracy of Compact Thermal Models of BGA and CPGA package styles was performed. For the CPGA special attention was given to the socket model. The compact model parameters were extracted using a standard optimization procedure to best reproduce the junction temperature and heat flows computed for the detailed models exposed to a reduced set of heat transfer coefficients on the prime lumped areas. Various resistance network topologies were assessed for each package style. Detailed (FE) isotropic board models with conductivities spanning three orders of magnitude were created to test the influence of board conductivity on CTM accuracy. The board models included fully detailed isotropic models of the 1S0P and 1S2P JEDEC standard thermal test boards.