Low cost and high performance p-doped triple-gate access transistor for embedded DRAM memory cell

A new triple-gate transistor, formed by recessing the oxide layer in the isolation trenches, without any other significant modification in the conventional planar transistor process flow, is evaluated as the access transistor of the 65 nm node embedded DRAM (eDRAM) memory cell. In addition to the own advantages of this structure (high on-state current (I_on), small Body Bias Effect (BBE), excellent short channel effects (SCE) immunity), this transistor shows a lower off-state current (I_off) and better mismatch characteristics than the conventional planar one, thanks to the adoption of a p-doped gate electrode.