MOSFET implant failure analysis using plane-view scanning capacitance microscopy coupled with nano-probing and TCAD modeling

Author

Hun-Seong Choi ; Yong-Woon Han ; Il-Sub Chung

Author_Institution

Anal. Sci. & Eng. Group, Samsung Electron., Yongin, South Korea

fYear

2014

fDate

June 30 2014-July 4 2014

Firstpage

5

Lastpage

8

Abstract

This paper presents MOSFET implant failure analysis using plane view scanning capacitance microscopy (PVSCM) at silicon substrate level. Failing transistors are characterized by nano-probing (NP) at contact level. The cause of failure was deduced from the combination of PVSCM, IV characteristics from NP measurement, and TEM cross-section analysis. Technology computer aided design (TCAD) simulation was implemented for failure modeling and SCM data verification. Failure analysis case studies of samples manufactured by 65 nm and 45 nm process are presented.

Keywords

MOSFET; failure analysis; semiconductor device models; technology CAD (electronics); transmission electron microscopy; IV characteristics; MOSFET implant failure analysis; NP measurement; PVSCM; SCM data verification; Si; TCAD modeling; TEM cross-section analysis; contact level; failing transistors; nanoprobing; plane-view scanning capacitance microscopy; silicon substrate level; size 45 nm; size 65 nm; technology computer aided design simulation; Capacitance; Doping; Scanning electron microscopy; Silicon; Substrates; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2014 IEEE 21st International Symposium on the

Conference_Location

Marina Bay Sands

ISSN

1946-1542

Print_ISBN

978-1-4799-3931-2

Type

conf

DOI

10.1109/IPFA.2014.6898128

Filename

6898128