Die crack mechanism study and improvement on 54ld SOIC EP package

There are multiple die crack incidents reported on 54ld SOIC EP (Exposed pad) packages from one SMT customer. Various analytical methods were employed in order to find the root cause of the die crack, including CSAM, X-Ray, 4 point bend test, SEM & fractography analysis, TherMorie analysis and digital modeling. A series of experimentations on silicon, packaging process and SMT PCB board design were carried out. The root cause of the die crack is concluded as that SMT process and PCB board design generate high thermo-mechanical stress onto EP package, exceeding low end of die strength distribution. Anti die crack solutions were identified including: improving silicon mechanical strength and reducing thermal mechanical stress of SMT process. Optimizing dicing saw process, adding Diama flow additive, changing dicing sequence reduced die crack ppm by 50%, adding SEZ etching after wafer backgrinding can further reduce die crack ppm by 99.8%. TherMorie measurement on different PCB designs indicated full flag solder pad design generates less thermal mechanical stress than 4 solder bar solder pad design with 60% package warpage reduction.