Organic TFT with SiO2-parylene gate dielectric stack and optimized pentacene growth temperature

We show that the performances of low cost pentacene-based organic thin-film-transistors can be optimized adjusting the pentacene growth temperature. A performance gain exceeding 10 is obtained if the pentacene is grown with a substrate temperature of 50degC instead 90degC. The saturation drain current is not a monotonic function of the pentacene growth temperature. C-V measurements performed in dark conditions show a negligible hysteresis, but the hysteresis is strongly enhanced if the C-V measurements are performed in light, indicating the presence of photon-activated border traps.