DocumentCode
235792
Title
Effects of sidewall scallops on the performance and reliability of filled copper and open tungsten TSVs
Author
Filipovic, Lado ; de Orio, R.L. ; Selberherr, Siegfried
Author_Institution
Inst. for Microelectron., Tech. Univ. Wien, Vienna, Austria
fYear
2014
fDate
June 30 2014-July 4 2014
Firstpage
321
Lastpage
326
Abstract
The effects of the presence of scallops along the sidewalls of filled (copper) and open (tungsten) TSVs are studied. The Bosch process is used in order to generate highly vertical deep trenches; however, the process results in scallops along the etched sidewalls. A model for the Bosch process is implemented in an in-house level set simulator in order to generate various TSV structures with small and large sidewall scallops. The resulting geometries are imported into a finite element tool in order to analyze the performance and reliability of the devices. The electrical parameters of the TSVs are shown to vary when scallops are present for both types of TSVs. In addition, the maximum thermo-mechanical stress increases in the presence of scallops, while the average stress along the interfaces remains relatively unchanged. Electromigration analyses were also performed on the structures in order to determine stress development during the early stages of operation. It was found that the filled TSV with scalloped sidewalls experiences a higher current density and suffers from increased stress, while the sidewall scallops do not cause variation in the stress of open tungsten TSVs. The open tungsten TSVs experience most Electromigration-induced stress in the connecting metal layers and not along the sidewall.
Keywords
copper; current density; electromigration; etching; finite element analysis; integrated circuit reliability; integrated circuit testing; isolation technology; stress analysis; thermal stresses; three-dimensional integrated circuits; tungsten; Bosch process; Cu; TSV structures; W; current density; electrical parameters; electromigration analyses; electromigration-induced stress; filled copper TSV; finite element tool; in-house level set simulator; open tungsten TSV; sidewall scallops; thermomechanical stress; Capacitance; Copper; Etching; Silicon; Stress; Through-silicon vias; Tungsten;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits (IPFA), 2014 IEEE 21st International Symposium on the
Conference_Location
Marina Bay Sands
ISSN
1946-1542
Print_ISBN
978-1-4799-3931-2
Type
conf
DOI
10.1109/IPFA.2014.6898137
Filename
6898137
Link To Document