Title :
Algorithms and VLSI implementation for block-matching motion estimation
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ., Hong Kong
Abstract :
Motion estimation is the most computationally intensive component of a video coding algorithm. It could consume as much as 75% of the total processing power of a video codec. Although various international video coding standards have adopted the block-matching approach for motion estimation, a designer can still have the freedom to choose a specific technique to find the motion vectors. Consequently, numerous techniques ranging from full search to simple fast search algorithms have been proposed and some of them have been implemented in VLSI chips. It should be emphasized that one of the most important requirements for an effective motion estimation algorithm is its ability to perform in real-time. The choice of a specific algorithm for implementation, however, depends very much on the intended application as well as the trade-offs between the desired performance and affordable complexity. In this paper, we first discuss what are the essential ingredients for an effective block-matching motion estimation, then briefly, describe what is the status of current technology, and finally, present some new activities in this vital area of research
Keywords :
VLSI; digital signal processing chips; image matching; motion estimation; video coding; DSP chips; VLSI implementation; block-matching motion estimation; video coding algorithms; Circuits; Costs; Motion estimation; Network address translation; Notice of Violation; Predictive coding; Telecommunications; Very large scale integration; Video codecs; Video compression;
Conference_Titel :
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2440-4
DOI :
10.1109/APCCAS.1994.514606