A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders

Parallel turbo decoding techniques to achieve high throughput have been extensively investigated in the literature. These techniques are commonly combined. In this case, the impact on the hardware complexity and on the throughput is usually only accurately determined at the end of the design process. Thus, the time to market is penalized and the probability of designing a sub optimal system increases. In this paper we address this problem by introducing a dedicated approach to efficiently explore the design space of parallel turbo decoder architectures. Using this approach, a tradeoff between the hardware complexity and the throughput can be established in the early stages of the architecture design process. Our approach considers especially memory conflict issues, as well as Soft-Input Soft-Output decoder architectures.