Reliability approach of high density Through Silicon Via (TSV)

Author

Frank, Thomas ; Chappaz, Cédrick ; Leduc, Patrick ; Arnaud, Lucile ; Moreau, Stéphane ; Thuaire, Aurélie ; El Farhane, Rebha ; Anghel, Lorena

Author_Institution

STMicroelectronics, Crolles, France

fYear

2010

fDate

8-10 Dec. 2010

Firstpage

321

Lastpage

324

Abstract

This paper focuses on the link between initial electrical resistance of Through Silicon Via (TSV), and possible failure occurring during Thermal Cycling Test (TCT) and electromigration (EM) tests. Physical analyses reveal the presence of a carbon impurity layer at bottom of the higher resistance TSVs. This impurity induces failure during TCT, but has no impact on EM time to failure distribution. We also discuss the relevance of different electrical resistance failure criterions after TCT for a single TSV.

Keywords

carbon; electric resistance; electromigration; failure analysis; integrated circuit reliability; three-dimensional integrated circuits; TSV; carbon impurity layer; electrical resistance; electromigration; failure distribution; high density through silicon via; reliability; thermal cycling test; Electromigration; Failure Criterion; Reliability; Thermal Cycling; Through Silicon Via (TSV); Void;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2010 12th

Conference_Location

Singapore

Print_ISBN

978-1-4244-8560-4

Electronic_ISBN

978-1-4244-8561-1

Type

conf

DOI

10.1109/EPTC.2010.5702655

Filename

5702655

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2358174