Design for reliability in via middle and via last 3-D chipstacks incorporating TSVs

Author

Trigg, A.D. ; Yu, Li Hong ; Yong Zhong Xiong ; Lin, Shi Jing ; Kuo, Cheng Cheng ; Khan, Navas ; Hwa, Teo Keng ; Shan, Gao

Author_Institution

Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore

fYear

2010

fDate

8-10 Dec. 2010

Firstpage

328

Lastpage

332

Abstract

Two test chips have been designed to determine the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). One of the chips uses via-middle technology while the other uses via-last technology. Both chips are fabricated in a commercial foundry using a 65 nm CMOS process. Both chips contain test structures designed to measure performance of transistors and other active devices, the resistance and electromigration performance of TSVs and microbumps, thermal performance, corrosion related to moisture ingress. This paper will focus on the reliability features of the chips, excluding the active devices.

Keywords

electromigration; integrated circuit reliability; three-dimensional integrated circuits; transistors; 3D chipstack; CMOS process; electromigration performance; microbump; size 65 nm; thermal performance; through silicon vias; transistor performance; via-last technology; via-middle technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2010 12th

Conference_Location

Singapore

Print_ISBN

978-1-4244-8560-4

Electronic_ISBN

978-1-4244-8561-1

Type

conf

DOI

10.1109/EPTC.2010.5702657

Filename

5702657