Title :
Back-end defect localization for 28nm FPGA
Author :
Ng, Jack Yi Jie ; Liew Chiun Ning ; Khoo Khai Ling
Author_Institution :
Bayan Lepas Technoplex, Altera Corp. (M), Bayan Lepas, Malaysia
fDate :
June 30 2014-July 4 2014
Abstract :
This paper presents two case studies, which are based on 28nm Field Programmable Logic Array (FPGA) bulk silicon technology, to highlight the novel approach on locating back-end interconnects and metallization defect by utilizing local software, which are Interconnect Test Generation (ITG) debugger and Functional Interface, then follow by extensive layout study, suspected defect node identification, parallel lapping and Scanning Emission Microscope (SEM) inspection.
Keywords :
field programmable gate arrays; integrated circuit reliability; logic arrays; logic testing; metallisation; FPGA; back end defect localization; back end interconnects; defect node identification; field programmable logic array bulk silicon technology; functional interface; interconnect test generation debugger; metallization defect; parallel lapping; scanning emission microscope inspection; size 28 nm; Decision support systems; Failure analysis; Integrated circuits;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2014 IEEE 21st International Symposium on the
Conference_Location :
Marina Bay Sands
Print_ISBN :
978-1-4799-3931-2
DOI :
10.1109/IPFA.2014.6898156
