Operational semantics for Verilog

We consider a non-trivial subset of Verilog HDL and construct an operational semantics for it. Only a handful of convenient but nonessential statements are left out for the sake of brevity. However, all challenging parts of the language, including Behavioural and RTL constructs, are considered. The semantics we give is fully parallel unlike the semantics built into most Verilog simulators. This allows us to eliminate all side effects caused by employing nondeterminism instead of parallelism. Another benefit of the parallelism in our framework is the ability to better model real hardware. Several healthiness conditions are proven to support the validity of the proposed semantics. We use these healthiness conditions to formally underpin our understanding of and increase our confidence in the semantics we give.