Double-gate pentacene TFTs with improved control in subthreshold region

Author

Cvetkovic, Nenad V. ; Tsamados, Dimitrios ; Sidler, Katrin ; Bhandari, Jyotshna ; Savu, Veronica ; Brugger, Juergen ; Ionescu, Adrian M.

Author_Institution

Nanoelectronic Devices Lab. (Nanolab), Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

205

Lastpage

208

Abstract

In this work a double-gate pentacene TFT architecture is presented. The devices are fabricated on a polyimide substrate using three aligned levels of stencil lithography along with standard photolithography, which enable a soft yet well-controlled device processing. The positive impact of the top gate voltage control on reducing the leakage current and significantly improving the subthreshold swing of the device is demonstrated. Moreover, this original design shows good promise for the enhancement of I_ON/I_OFF TFT characteristics.

Keywords

leakage currents; organic semiconductors; photolithography; semiconductor thin films; thin film transistors; duble-gate pentacene TFT; leakage current; photolithography; polyimide substrate; stencil lithography; subthreshold swing; top gate voltage; Dielectric substrates; Electrodes; Laboratories; Leakage current; Lithography; Nanoscale devices; Organic thin film transistors; Pentacene; Polyimides; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European

Conference_Location

Athens

ISSN

1930-8876

Print_ISBN

978-1-4244-4351-2

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2009.5331352

Filename

5331352