Wafer-level fault isolation approach to debug integrated circuits JTAG failures

Author

Goh, S.H. ; You, G.F. ; Yeoh, B.L. ; Hu Hao ; Chung, N.L. ; Yap, C.P. ; Lam, James

Author_Institution

Technol. Dev., New Technol. Prototyping, GLOBALFOUNDRIES, Singapore, Singapore

fYear

2014

fDate

June 30 2014-July 4 2014

Firstpage

30

Lastpage

34

Abstract

Boundary scan test failures in the early phase of integrated circuit device yield engineering suggest fundamental manufacturing weaknesses and require fast response to fix the I/O connectivity, without which, chip functionality cannot be validated further. This paper presents a complete wafer-level workflow for JTAG-based boundary scan debug. We also show how a tester-based fault isolation technique called frequency mapping can be extended to JTAG data registers shift failures with the help of basic JTAG test methodology knowledge.

Keywords

boundary scan testing; design for testability; failure analysis; fault diagnosis; integrated circuit design; integrated circuit reliability; integrated circuit testing; I/O connectivity; JTAG data registers shift failures; JTAG test methodology knowledge; JTAG-based boundary scan debug; circuit device yield engineering; design-for-test technique; frequency mapping; integrated circuit JTAG failure debugging; tester-based fault isolation technique; wafer-level fault isolation approach; wafer-level workflow; Decision support systems; Failure analysis; Integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2014 IEEE 21st International Symposium on the

Conference_Location

Marina Bay Sands

ISSN

1946-1542

Print_ISBN

978-1-4799-3931-2

Type

conf

DOI

10.1109/IPFA.2014.6898176

Filename

6898176