Thermal modelling of the emerging multi-chip packages

The thermal dissipation challenges that are seen today with single-chip components will only be magnified with the introduction of System in Package devices. The traditional compact representation of IC components that utilises the generation of thermal resistance networks for modelling their complex mechanical structure has been revised to allow the development of new model families for multi-chip packages. The present multi-resistor network modelling approach, dedicated to multi-chip packages, is based on the methodology proposed by the DELPHI consortium that has been improved by the use of genetic algorithm fitting technique and superposition principle. This approach appears very powerful and able to supply accurate compact thermal models for large package and chip geometries, complex or not. If the use of DELPHI methodology is to be extended to stacked multi-chip packages the thermal modeling of asymmetric side-by-side chip packages will demand better definition of the package external surface heat exchange characteristics. The known practice of surface subdivision, such as upper chip area, which are normally used for the compact thermal models, have to be revised. In order to maintain the accuracy between compact thermal model results and detailed thermal model results for, amongst others, System In Package devices the next phase of work should address optimization of the surface subdivisions for each face of the model.