Hierarchical gate-level verification of speed-independent circuits

Author

Roig, Oriol ; Cortadella, Jordi ; Pastor, Enric

Author_Institution

Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain

fYear

1995

fDate

30-31 May 1995

Firstpage

128

Lastpage

137

Abstract

This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification

Keywords

asynchronous circuits; computational complexity; logic testing; complex gates; hierarchical gate-level verification; speed-independent circuits; state signals; time complexity; Asynchronous circuits; Clocks; Computational efficiency; Computer architecture; Digital systems; Flip-flops; Hazards; Performance analysis; State-space methods; Sufficient conditions;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on

Conference_Location

London

Print_ISBN

0-8186-7098-3

Type

conf

DOI

10.1109/WCADM.1995.514650

Filename

514650