DocumentCode :
2359016
Title :
Testing self-timed circuits using partial scan
Author :
Khoche, Ajay ; Brunvand, Erik
Author_Institution :
Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
fYear :
1995
fDate :
30-31 May 1995
Firstpage :
160
Lastpage :
169
Abstract :
This paper presents a partial scan method for testing both the control and data path parts of macromodule based self-timed circuits for stuck-at faults. Compared with other proposed test methods for testing control paths in self-timed circuits, this technique offers better fault coverage under a stuck-at input model than methods using self-checking properties, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in the control path in this partial scan environment. The partial scan approach has also been applied to data paths, where structural analysis is used to select which latches should be made scannable to break cycles in the circuit. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements in the control and data paths being made scannable
Keywords :
asynchronous circuits; logic testing; sequential circuits; data paths; partial scan; partial scan environment; self-timed circuits; sequential network; Asynchronous circuits; Automatic testing; Centralized control; Circuit faults; Circuit testing; Cities and towns; Clocks; Computer science; Delay; Protocols;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on
Conference_Location :
London
Print_ISBN :
0-8186-7098-3
Type :
conf
DOI :
10.1109/WCADM.1995.514653
Filename :
514653
Link To Document :
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