DocumentCode
2359019
Title
Model checking UML statecharts
Author
Dong, Wei ; Wang, Ji ; Qi, Xuan ; Qi, Zhi-Chang
Author_Institution
Nat. Lab. for Parallel & Distributed Process., Changsha, China
fYear
2001
fDate
4-7 Dec. 2001
Firstpage
363
Lastpage
370
Abstract
Unified Modeling Language (UML) has been widely used in software development. Verifying if an UML model meets the required properties has become a key issue. Model checking is an important technology of automatic formal verification to ensure the correctness of design specifications. An approach of model checking UML statecharts is given in this paper At first, the brief syntax and semantics of UML statecharts are described. Then, the way of how UML statecharts is structurally expressed by extended hierarchical automaton and the labeled transition system are defined. The correctness of operational semantics of UML statecharts can be ensured through finding the maximal non-conflict transition set. For the system with infinite runs, the operational semantics can be mapped to a Buchi automaton and linear temporal logic properties of the system can be verified based on the automata theory of model checking. The paper also presents the method of verifying complex system consist of multiple objects modeled by statecharts and collaboration diagram.
Keywords
automata theory; program verification; specification languages; temporal logic; Buchi automaton; UML statecharts; Unified Modeling Language; automatic formal verification; design specifications; extended hierarchical automaton; labeled transition system; linear temporal logic properties; model checking; Automata; Collaboration; Concurrent computing; Distributed processing; Formal verification; Laboratories; Logic; Power system modeling; Programming; Unified modeling language;
fLanguage
English
Publisher
ieee
Conference_Titel
Software Engineering Conference, 2001. APSEC 2001. Eighth Asia-Pacific
ISSN
1530-1362
Print_ISBN
0-7695-1408-1
Type
conf
DOI
10.1109/APSEC.2001.991503
Filename
991503
Link To Document