Effect of substrate warpage on flip chip BGA thermal stress simulation

In this work, a new empirical method is proposed to incorporate the initial substrate warpage into package stress simulation. As a first step, the bare substrate strip warpage characteristics were mapped. The out-of-plane displacements of the substrate strips were measured as a function of temperature using shadow moire technique. It was observed that the warpage values of the bare substrate vary predominantly along the length of the strip. Units located at the substrate corners and edges exhibited higher warpage compared to units in the strip center. The higher warpage at units located at the substrate edge could impact the flip chip assembly process and also the stresses at the 1st level interconnect. 2 locations representing the maximum and minimum warpage values were identified and the warpage profiles mapped as a function of temperature. These warpage profiles were used in simulation to create an initial substrate pre-warp condition for subsequent package stress simulation. Simulation results showed that the maximum von Mises stress for the unit with higher initial substrate warpage was up to 2x more compared to a relatively flat substrate. This was validated with actual observations and failures from assembly. With the trend towards adopting larger substrate strip sizes, reduction of flip chip pitches and introduction of ultralow k devices, the impact of substrate warpage on the resultant package stress could be even more critical. The proposed methodology to include the initial substrate warpage into the FEA simulation will improve the accuracy of stress prediction.