Quadrant-based XYZ dimension order routing algorithm for 3-D Asymmetric Torus Routing Chip (ATRC)

The conventional two-dimensional (2-D) integrated circuit (IC) has limited scope for floor planning and therefore limits the performance improvements resulting from the Network-on-Chip (NoC) paradigm. Three Dimensional (3-D) ICs are able to obtain significant performance benefits over 2-D ICs based on the electrical and mechanical properties resulting from the new geometrical arrangement (topology). The arrangement of 3-D also offers opportunities for new circuit architecture based on the geometric capacity that provide greater numbers of interconnections among multi-layer active circuits. The emerging 3-D VLSI Integration and process technologies allow the new design opportunities in 3-D NoC. The 3-D NoC can reduce significant amount of wire length for local and global interconnects. In this paper, we have proposed an efficient 3-D Asymmetric Torus routing algorithm for NoC router. The 3-D torus has constant node degree, recursive structure, simple communication algorithms, and good scalability. A Quadrant-based XYZ dimension order routing algorithm is proposed to build up the 3-D Asymmetric Torus NoC router. The algorithm partitions the Torus space into quadrants and selects the nearest wrap-around edge to connect the destination node. Thus, the presented algorithm guarantees minimal paths to each destination based on routing regulations. The complexity of the compared with the traditional XYZ algorithm and the comparison results show that the quadrant-based router has shorter path length. This paper presents a Register Transfer Logic (RTL) simulation model of Quadrant-based XYZ dimension order routing algorithm for 3-D ATRC written in Verilog. The model represents the functional behavior of the routing chip down to the flit (byte) level. The 3-D TRC has achieved a maximum operating frequency 750 MHz on Xilinx Vertex-6.