DocumentCode
2359057
Title
ECSTAC: a fast asynchronous microprocessor
Author
Morton, Shannon V. ; Appleton, Sam S. ; Liebelt, Michael J.
Author_Institution
Southbank Univ., London, UK
fYear
1995
fDate
30-31 May 1995
Firstpage
180
Lastpage
189
Abstract
This paper introduces some of the principal design issues encountered in the development of a prototype asynchronous microprocessor using a two-phase communication strategy. These issues include the control of the processor pipeline, register tagging, branch techniques, and the implementation of caches. The arbitration and synchronisation methods employed in the design are discussed, and expected performance figures based on block simulation results are given
Keywords
asynchronous circuits; logic design; microprocessor chips; ECSTAC; asynchronous microprocessor; block simulation; branch techniques; caches; processor pipeline; register tagging; two-phase communication; Circuits; Clocks; Communication system control; Control systems; Delay; Microprocessors; Pipelines; Protocols; Prototypes; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on
Conference_Location
London
Print_ISBN
0-8186-7098-3
Type
conf
DOI
10.1109/WCADM.1995.514655
Filename
514655
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